The present invention relates to the field of a networking communication system, and more particularly to implementing an error correction code scheme when the bandwidth of the memory permits and implementing a parity scheme when the bandwidth of the memory does not permit implementing the error correction code scheme.
A packet switching network has switching points or nodes for transmission of data among senders and receivers connected to the network. The switching performed by these switching points is in fact the action of passing on packets or xe2x80x9cframesxe2x80x9d of data received by a switching point or node to a further node in the network. Such switching actions are the means by which communication data is moved through the packet switching network.
Each node may comprise a packet processor configured to process packets or frames of data. The packet processor may comprise a data storage unit, e.g., Double Data Rate Static Random Access Memory (DDR SRAM), configured with a plurality of buffers to store frame data. Each frame of data may be associated with a Frame Control Block (FCB) configured to describe the corresponding frame of data. Each FCB associated with a frame of data may be associated with one or more Buffer Control Blocks (BCBs). Each BCB associated with an FCB may be associated with a buffer in the data storage unit. The BCB associated with an FCB may be configured to describe the associated buffer. Typically, FCBs and BCBs comprise various fields of information where the fields of information in FCBs and BCBs are each supplied by a separate memory, e.g., Quadruple Data Rate Static Random Access Memory (QDR SRAM), in the packet processor. That is, the fields of information in FCBs and BCBs may be obtained by accessing a separate memory, e.g., QDR SRAM, in the packet processor.
Errors may result in writing and/or reading the information in the fields of the control blocks, e.g., FCBs, BCBs. A common method of detecting errors in the fields of control blocks, e.g., FCBs, BCBs, may be to reserve a bit commonly referred to as a parity bit in one of the bits of the control block. The scheme of reserving a parity bit in one of the bits of the control block to indicate errors may be referred to as the parity bit scheme. The parity bit scheme simply detects errors but does not correct errors.
A method of detecting and to some extent correcting errors in the fields of control blocks, e.g., FCBs, BCBs, may be to implement an Error Correction Code (ECC) scheme. The ECC scheme requires the reservation of more bits of information, e.g., 6 bits, in the control blocks than the parity bit scheme, e.g., 1 bit, to store the code of the ECC scheme. However, control blocks, e.g., FCBs, BCBs, may not have enough bits available for storing the ECC scheme.
It would therefore be desirable to implement the ECC scheme when the control blocks, e.g., FCBs, BCBs, comprise enough available bits to store the code of the ECC scheme and implement the parity bit scheme when the control blocks, e.g., FCBs, BCBs, do not comprise enough available bits to store the code of the ECC scheme.
The problems outlined above may at least in part be solved in some embodiments by implementing the parity bit scheme in the control blocks, e.g., Frame Control Blocks (FCBs), Buffer Control Blocks (BCBs), when the FCBs are associated with frames of data, i.e., when the FCBs do not comprise enough available bits to store the code for the Error Correction Code (ECC) scheme. FCBs that are not associated with a frame of data may store the code for the ECC scheme as there are available bits to store the code for the ECC scheme. BCBs that are not associated with a buffer may store the code for the ECC scheme as there are available bits to store the code for the ECC scheme.
In one embodiment, a system comprises a processor configured to process frames of data. The processor comprises a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each buffer control block associated with a frame control block may be associated with a buffer configured to store frame data. The processor may further comprise a first queue configured to store one or more frame control blocks associated with one or more frames of data. The processor may further comprise a second queue configured to store one or more frame control blocks not associated with a frame of data. The processor may further comprise a third queue configured to store one or more buffer control blocks not associated with a particular buffer of the plurality of buffers. The one or more frame control blocks associated with one or more frames of data in the first queue comprise a bit for storing a parity value as there are not available bits for storing the code of the error correction code scheme. Each of the one or more buffer control blocks associated with each of the one or more frame control blocks in the first queue comprises a bit for storing the parity bit as there are not available bits for storing the code of the error correction code scheme. The one or more frame control blocks in the second queue comprise a plurality of bits for storing a code of an error correction code scheme. The one or more buffer control blocks in the third queue comprise a plurality of bits for storing the code of the error correction code scheme.
In another embodiment of the present invention, a method for using a parity bit in a frame control block associated with a frame of data to be transmitted comprises the step of reading the frame control block associated with the frame of data to be transmitted where the frame control block is configured to describe the frame of data. The method further comprises determining whether the parity bit in the frame control block indicated an error. If the parity bit in the frame control block indicated an error then one or more frame control blocks following the frame control block with the parity bit that indicated an error in a first queue may be lost in the processor. In one embodiment, the one or more frame control blocks that are lost in the processor may be located by a background mechanism and returned to a second queue for storage. If the parity bit in the frame control block did not indicate an error, then the first buffer control block associated with the frame control block is read. A determination is made as to whether the parity bit in the first Buffer Control Block (BCB) indicated an error. If the parity bit in the first BCB indicated an error, then the one or more BCBs following the first BCB may be lost in the processor. In one embodiment, the one or more BCBs that are lost in the processor may be located by a background mechanism and returned to a third queue for storage. If the parity bit in the first BCB did not indicate an error, then a determination is made as to whether the first BCB was the last BCB associated with the frame control block. If the first BCB is the last BCB then a next frame control block may be read associated with a next frame of data to be transmitted. If the first BCB is not the last BCB associated with the frame control block, then a next BCB may be read. The above steps involving the first BCB may be repeated with the next BCB.
For example, a determination may be made as to whether the parity bit in the next BCB indicated an error. If the parity bit in the next BCB indicated an error, then the one or more BCBs following the next BCB may be lost in the processor. In one embodiment, the one or more BCBs that are lost in the processor may be located by a background mechanism and returned to a third queue for storage. If the parity bit in the next BCB did not indicate an error, then a determination may be made as to whether the next BCB was the last BCB associated with the frame control block. If the next BCB is the last BCB then a next frame control block may be read associated with a next frame of data to be transmitted. If the next BCB is not the last BCB associated with the frame control block, then the BCB following the next BCB may be read. The above steps may be repeated for each of the BCBs following the next BCB.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.